FIG. 1 is a diagram showing an example of a hard bit error. In the example shown, diagram 100 shows two tracks before a write. In the state shown, track N (110a) is blank and track N+1 (112a) includes the bit sequence [0 0 1 0 0 0]. Track N is then written and diagram 150 shows the state of the two tracks after the write. After the write, track N (110b) includes the bit sequence [0 0 0 0 0 0]. Although track N+1 was not intended to be written to, bit 114b in track N+1 (112b) flipped from a 1 (see, e.g., 114a) to a 0 (see, e.g., 114b). This is an example of a hard bit error. Correcting hard bit errors is very difficult for a soft decision error correction decoder. Although track N+1 was not intended to be written, a 0 was effectively written to bit 114b and so bit 114b is indistinguishable to an error correction decoder from a genuine and/or intended 0. As tracks get closer to each other and/or as the width of each track gets thinner, hard bit errors are becoming more common. New techniques which improve error correction performance in the presence of hard bit errors would be desirable.